1. Field of the Invention
This invention generally relates to integrated circuit (IC) memory fabrication and, more particularly, to a high-density resistor random access memory (RRAM) array structure and fabrication process.
2. Description of the Related Art
Conventionally, RRAMs are fabricated on bulk silicon. As is well known in the art, there is a relatively high degree and leakage current and capacitance associated with memory cells fabricated on bulk silicon, that translates into degraded read and write times. However, applications are beginning to demand that RRAM programming pulse widths be as narrow as 10 nanoseconds (ns). Silicon-on-insulator (SOI) CMOS devices are known to have a significantly higher speed than corresponding bulk silicon devices. Therefore, a SOI substrate RRAM would be desirable for very high-speed memory circuits.
An SOI substrate is made from a silicon (Si) layer that overlies an insulator material, such as sapphire or oxide. The insulation layer of an SOI substrate completely isolates associated NMOS and PMOS transistors, to prevent the occurrence of latch-up. Further, the device channel doping need not overcompensate, and the diffusion regions do not have bottom junctions. All these factor lead to a reduction in parasitic capacitance.
In a pending application entitled, DUAL-TRENCH ISOLATED CROSSPOINT MEMORY ARRAY AND METHOD FOR FABRICATING SAME, invented by Hsu et al., Ser. No. 10/350,643, now U.S. Pat. No. 6,875,651, filed Jan. 23, 2003, and which is incorporated herein by reference, a vertical one resistor/one diode (1R1D) structure is described that can be used to form a high density memory array. The structure forms P+ on a highly conductive buried N+ bit line. The resulting thickness of the P+N junction, however, is at least 500 nanometers (nm), and not suitable for SOI processes.
FIG. 1 is a partial cross-sectional view of a dual trench isolated 1R1D RAM on bulk silicon wafer (pending art). A shallow trench extends, at least partially, into the P+ layer to avoid the leakage current drawn from the bottom electrode, to the N+ bit line. The conductivity of the N+ bit line is no higher than 1 kilo-ohm (Kohm) per square if the thickness is less than 500 nm. Therefore, the minimum thickness of the SOI film has to be in the order of 500 nm in order to provide low parasitic resistance. However, the thickness of a periphery circuit area can be much thinner than that of the memory area, and this thickness difference is too large for a state-of-the-art lithograph tool to handle.
It would be advantageous if a process were developed to increase the density of memory cells formed in an SOI RRAM array.
It would be advantageous if an SOI RRAM array could be formed to take advantage of the minimum available feature size.